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| CYV15G0204TRB Independent Clock HOTLink IITM Dual Serializer and Dual Reclocking Deserializer Features * Second-generation HOTLink(R) technology * Compliant to SMPTE 292M and SMPTE 259M video standards * Dual-channel video serializer plus dual channel video reclocking deserializer -- 195- to 1500-Mbps serial data signaling rate -- Simultaneous operation at different signaling rates * Supports reception of either 1.485 or 1.485/1.001 Gbps data rate with the same training clock * Supports half-rate and full-rate clocking * Internal phase-locked loops (PLLs) with no external PLL components * Selectable differential PECL-compatible serial inputs -- Internal DC-restoration * Redundant differential PECL-compatible serial outputs -- No external bias resistors required -- Signaling-rate controlled edge-rates * * * * -- Internal source termination Synchronous LVTTL parallel interface JTAG boundary scan Built-In Self-Test (BIST) for at-speed link testing Link Quality Indicator -- Analog signal detect -- Digital signal detect * Low-power 2.5W @ 3.3V typical * Single 3.3V supply * Thermally enhanced BGA * Pb-Free package option available * 0.25 BiCMOS technology Functional Description The CYV15G0204TRB Independent Clock HOTLink IITM Dual Serializer and Dual Reclocking Deserializer is a point-to-point or point-to-multipoint communications building block enabling transfer of data over a variety of high-speed serial links including SMPTE 292M and SMPTE 259M video applications. It supports signaling rates in the range of 195 to 1500 Mbps per serial link. All transmit and receive channels are independent and can operate simultaneously at different rates. Each transmit channel accepts 10-bit parallel characters in an Input Register and converts them to serial data. Each receive channel accepts serial data and converts it to 10-bit parallel characters and presents these characters to an Output Register. The received serial data can also be reclocked and retransmitted through the reclocker serial outputs. Figure 1 illustrates typical connections between independent video co-processors and corresponding CYV15G0204TRB chips. The CYV15G0204TRB satisfies the SMPTE 259M and SMPTE 292M compliance as per SMPTE EG34-1999 Pathological Test Requirements. As a second-generation HOTLink device, the CYV15G0204TRB extends the HOTLink family with enhanced levels of integration and faster data rates, while maintaining serial-link compatibility (data and BIST) with other HOTLink devices. Each transmit (TX) channel of the CYV15G0204TRB HOTLink II device accepts scrambled 10-bit transmission characters. These characters are serialized and output from dual Positive ECL (PECL) compatible differential transmission-line drivers at a bit-rate of either 10- or 20-times the input reference clock for that channel. Independent Channel CYV15G0204TRB Device Figure 1. HOTLink IITM System Connections Independent Channel CYV15G0204TRB Device Reclocked Outputs 10 10 10 Serial Links 10 10 10 Reclocked Outputs Cypress Semiconductor Corporation Document #: 38-02101 Rev. *C * 198 Champion Court * San Jose, CA 95134-1709 * 408-943-2600 Revised May 2, 2007 [+] Feedback Video Coprocessor 10 Video Coprocessor CYV15G0204TRB Each receive (RX) channel of the CYV15G0204TRB HOTLink II device accepts a serial bit-stream from one of two selectable PECL-compatible differential line receivers, and using a completely integrated Clock and Data Recovery PLL, recovers the timing information necessary for data reconstruction. The recovered bit-stream is reclocked and retransmitted through the reclocker serial outputs. Also, the recovered serial data is deserialized and presented to the destination host system. Each transmit and receive channel contains an independent BIST pattern generator and checker, respectively. This BIST hardware allows at-speed testing of the high-speed serial data paths in each transmit and receive section, and across the interconnecting links. The CYV15G0204TRB is ideal for SMPTE applications where different data rates and serial interface standards are necessary for each channel. Some applications include multi-format routers, switchers, format converters, SDI monitors, cameras, and camera control units. CYV15G0204TRB Logic Block Diagram REFCLKA RXDC[9:0] RXDD[9:0] TRGCLKC TXDA[9:0] x10 Phase Align Buffer Serializer x10 Phase Align Buffer Serializer TXDB[9:0] x10 x10 Deserializer Deserializer TX TX Reclocker RX Reclocker RX ROUTC1 ROUTC2 ROUTD1 ROUTD2 TOUTB1 TOUTB2 TOUTA1 TOUTA2 INC1 INC2 Document #: 38-02101 Rev. *C IND1 IND2 TRGCLKD REFCLKB Page 2 of 31 [+] Feedback CYV15G0204TRB Serializer Path Block Diagram REFCLKA+ REFCLKA- TXRATEA SPDSELA TXCLKOA TXERRA TXCLKA TXCKSELA 0 1 Character-Rate Clock A PABRSTA Bit-Rate Clock A = Internal Signal TransmitPLL PLL Transmit Clock Multiplier A Clock Multiplier OEA[2..1] RESET TXBISTA OEA[2..1] Phase-Align Phase-Align Buffer Buffer BIST LFSR Input Register TXDA[9:0] 10 10 10 10 Shifter OUTA1+ OUTA1- OUTA2+ OUTA2- REFCLKB+ REFCLKB- TXRATEB SPDSELB TXCLKOB TXERRB TXCLKB TXCKSELB 0 1 Character-Rate Clock B PABRSTB Bit-Rate Clock B TransmitPLL PLL Transmit Clock Multiplier B Clock Multiplier OEB[2..1] TXBISTB OEB[2..1] Phase-Align Phase-Align Buffer Buffer BIST LFSR Input Register TXDB[9:0] 10 10 10 10 Shifter OUTB1+ OUTB1- OUTB2+ OUTB2- Document #: 38-02101 Rev. *C Page 3 of 31 [+] Feedback CYV15G0204TRB Reclocking Deserializer Path Block Diagram TRGRATEC TRGCLKC SDASEL[2..1]C[1:0] LDTDEN = Internal Signal RESET TRST x2 JTAG Boundary Scan Controller TMS TCLK TDI TDO BIST LFSR Output Register INSELC INC1+ INC1- INC2+ INC2- ULCC SPDSELC RXPLLPDC Shifter Receive Signal Monitor Clock & Data Recovery PLL LFIC 10 10 10 RXDC[9:0] BISTSTC /2 RXBISTC[1:0] RXRATEC RXCLKC+ RXCLKC- Recovered Character Clock Recovered Serial Data ROE[2..1]C Reclocker Output PLL Clock Multiplier C RECLKOC REPDOC TRGRATED TRGCLKD SDASEL[2..1]D[1:0] LDTDEN Character-Rate Clock C Register ROE[2..1]C ROUTC1+ ROUTC1- ROUTC2+ ROUTC2- x2 BIST LFSR Output Register INSELD IND1+ IND1- IND2+ IND2- ULCD SPDSELD RXPLLPDD Shifter Receive Signal Monitor Clock & Data Recovery PLL LFID 10 10 10 RXDD[9:0] BISTSTD /2 RXBISTD[1:0] RXRATED RXCLKD+ RXCLKD- Recovered Character Clock Recovered Serial Data ROE[2..1]D Reclocker Output PLL Clock Multiplier D RECLKOD REPDOD Character-Rate Clock D Register ROE[2..1]D ROUTD1+ ROUTD1- ROUTD2+ ROUTD2- Document #: 38-02101 Rev. *C Page 4 of 31 [+] Feedback CYV15G0204TRB Device Configuration and Control Block Diagram TXRATE[A..B] TXCKSEL[A..B] PABRST[A..B] TOE[2..1][A..B] TXBIST[A..B] RXRATE[C..D] SDASEL[2..1][C..D][1:0] TRGRATE[C..D] RXPLLPD[C..D] RXBIST[C..D][1:0] ROE[2..1][C..D] = Internal Signal WREN ADDR[3:0] DATA[6:0] Device Configuration and Control Interface Document #: 38-02101 Rev. *C Page 5 of 31 [+] Feedback CYV15G0204TRB Pin Configuration (Top View)[1] 1 A B C D E F G H J K L M N P R T U V W Y IN C1- IN C1+ TDI 2 ROUT C1- ROUT C1+ TMS 3 IN C2- IN C2+ INSELC 4 ROUT C2- ROUT C2+ 5 VCC VCC VCC VCC 6 IN D1- IN D1+ ULCD 7 ROUT D1- ROUT D1+ ULCC 8 GND 9 IN D2- IN D2+ DATA [6] DATA [5] 10 ROUT D2- ROUT D2+ DATA [4] DATA [3] 11 GND 12 TOUT A1- TOUT A1+ DATA [0] 13 GND 14 GND 15 TOUT A2- TOUT A2+ SPD SELD 16 VCC VCC VCC VCC 17 VCC NC 18 TOUT B1- TOUT B1+ TRST 19 VCC NC 20 TOUT B2- TOUT B2+ TDO GND NC GND NC VCC VCC VCC GND DATA [2] DATA [1] GND NC LDTD EN GND TCLK RESET INSELD VCC SPD SELC GND GND GND GND NC NC VCC VCC SCAN TMEN3 EN2 VCC VCC VCC VCC VCC VCC RX DC[8] RX DC[9] WREN VCC GND VCC GND NC NC TX CLKOB SPD SELA NC GND SPD SELB NC NC GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC RX DC[4] RX DC[5] RX DC[6] TRG CLKC- TRG CLKC+ RX DC[7] GND GND NC NC NC NC LFIC GND NC NC NC TX DB[6] TX CLKB VCC GND RE PDOC REF REF CLKB+ CLKB- TX ERRB GND GND GND GND GND GND GND RX DC[3] BIST STC RX DC[2] RX DC[1] RX DC[0] TX DB[5] TX DB[1] TX DB[4] TX DB[0] TX DB[3] TX DB[9] TX DB[2] TX DB[7] RE RX RX CLKOC CLKC+ CLKC- VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC LFID VCC RX DD[8] RX CLKD- RX CLKD+ VCC VCC VCC VCC RX DD[4] RX DD[5] RX DD[6] RX DD[7] RX DD[3] RX DD[1] RX DD[0] RX DD[2] GND TX DA[9] BIST STD ADDR [3] RE CLKOD ADDR TRG [0] CLKD- TX DA[1] GND TX DA[4] TX DA[3] TX DA[2] TX DA[0] TX DA[8] TX DA[7] TX DA[6] TX DA[5] VCC VCC VCC VCC NC TX DB[8] NC NC GND ADDR TRG TX [2] CLKD+ CLKOA ADDR [1] GND NC NC NC NC GND NC TX ERRA GND NC REF CLKA+ NC NC RX DD[9] GND NC TX CLKA NC GND RE REF PDOD CLKA- NC NC Note 1. NC = Do not connect. Document #: 38-02101 Rev. *C Page 6 of 31 [+] Feedback CYV15G0204TRB Pin Configuration (Bottom View)[1] 20 A B C D E F G H J K L M N P R T U V W Y TOUT B2- 19 VCC 18 TOUT B1- 17 VCC 16 VCC 15 TOUT A2- 14 GND 13 GND 12 TOUT A1- 11 GND 10 ROUT D2- 9 IN D2- 8 GND 7 ROUT D1- 6 IN D1- 5 VCC 4 ROUT C2- 3 IN C2- 2 ROUT C1- 1 IN C1- TOUT B2+ NC TOUT B1+ NC VCC TOUT A2+ NC GND TOUT A1+ NC ROUT D2+ IN D2+ GND ROUT D1+ IN D1+ VCC ROUT C2+ IN C2+ ROUT C1+ IN C1+ TDO GND TRST LDTD EN VCC SPD SELD NC GND DATA [0] DATA [2] DATA [4] DATA [6] GND ULCC ULCD VCC VCC INSELC TMS TDI TMEN3 SCAN EN2 VCC NC VCC NC GND GND GND DATA [1] DATA [3] DATA [5] GND SPD SELC VCC VCC VCC INSELD RESET TCLK VCC VCC VCC VCC VCC VCC VCC VCC NC TX CLKOB NC NC VCC VCC RX DC[9] RX DC[8] NC SPD SELA NC SPD SELB GND GND WREN GND GND GND GND GND GND GND GND GND NC NC NC NC GND GND GND GND NC NC NC NC GND GND TRG CLKC- RX DC[4] TX DB[6] NC NC NC GND LFIC TRG CLKC+ RX DC[5] TX CLKB TX ERRB REF REF CLKB- CLKB+ RE PDOC VCC RX DC[7] RX DC[6] GND GND GND GND GND GND GND GND TX DB[2] TX DB[3] TX DB[4] TX DB[5] RX DC[0] RX DC[1] RX DC[2] RX DC[3] TX DB[7] TX DB[9] TX DB[0] TX DB[1] RX RX RE CLKC- CLKC+ CLKOC BIST STC VCC VCC VCC VCC VCC VCC VCC VCC NC NC TX DB[8] NC VCC TX DA[8] TX DA[4] GND TX DA[1] TRG ADDR CLKD- [0] TX DA[9] GND RX DD[3] RX DD[4] VCC VCC VCC VCC VCC NC NC NC NC VCC TX DA[7] TX DA[3] GND TX TRG ADDR CLKOA CLKD+ [2] BIST STD GND RX DD[1] RX DD[5] VCC RX DD[8] VCC VCC VCC NC NC REF CLKA+ NC VCC TX DA[6] TX DA[2] GND TX ERRA NC ADDR [1] ADDR [3] GND RX DD[0] RX DD[6] VCC RX CLKD- LFID VCC VCC NC NC REF RE CLKA- PDOD VCC TX DA[5] TX DA[0] GND NC TX CLKA NC RE CLKOD GND RX DD[2] RX DD[7] VCC RX CLKD+ RX DD[9] VCC VCC Document #: 38-02101 Rev. *C Page 7 of 31 [+] Feedback CYV15G0204TRB Pin Definitions CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer Name TXDA[7:0] TXDB[7:0] I/O Characteristics Signal Description LVTTL Input, synchronous, sampled by the associated TXCLKx or REFCLKx[2] LVTTL Output, synchronous to REFCLKx [3], asynchronous to transmit channel enable / disable, asynchronous to loss or return of REFCLKx Transmit Data Inputs. TXDx[9:0] data inputs are captured on the rising edge of the transmit interface clock. The transmit interface clock is selected by the TXCKSELx latch via the device configuration interface. Transmit Path Data and Status Signals TXERRA TXERRB Transmit Path Error. TXERRx is asserted HIGH to indicate detection of a transmit Phase-Align Buffer underflow or overflow. If an underflow or overflow condition is detected, TXERRx, for the channel in error, is asserted HIGH and remains asserted until the transmit Phase-Align Buffer is re-centered with the PABRSTx latch via the device configuration interface. When TXBISTx = 0, the BIST progress is presented on the associated TXERRx output. The TXERRx signal pulses HIGH for one transmit-character clock period to indicate a pass through the BIST sequence once every 511 character times. TXERRx is also asserted HIGH, when any of the following conditions is true: * The TXPLL for the associated channel is powered down. This occurs when OE2x and OE1x for a given channel are both disabled by setting OE2x = 0 and OE1x = 0. * The absence of the REFCLKx signal. Transmit Path Clock Signals REFCLKA REFCLKB Differential LVPECL Reference Clock. REFCLKx clock inputs are used as the timing references for the transmit PLL. These input clocks may also be selected to clock the transmit parallel or single-ended interface. When driven by a single-ended LVCMOS or LVTTL clock source, connect LVTTL input clock the clock source to either the true or complement REFCLKx input, and leave the alternate REFCLKx input open (floating). When driven by an LVPECL clock source, the clock must be a differential clock, using both inputs. LVTTL Clock Input, internal pull-down Transmit Path Input Clock. When configuration latch TXCKSELx = 0, the associated TXCLKx input is selected as the character-rate input clock for the TXDx[9:0] input. In this mode, the TXCLKx input must be frequency-coherent to its associated TXCLKOx output clock, but may be offset in phase by any amount. Once initialized, TXCLKx is allowed to drift in phase as much as 180 degrees. If the input phase of TXCLKx drifts beyond the handling capacity of the Phase Align Buffer, TXERRx is asserted to indicate the loss of data, and remains asserted until the Phase Align Buffer is initialized. The phase of the TXCLKx input clock relative to its associated REFCLKx is initialized when the configuration latch PABRSTx is written as 0. When the associated TXERRx is deasserted, the Phase Align Buffer is initialized and input characters are correctly captured. Transmit Clock Output. TXCLKOx output clock is synthesized by each channel's transmit PLL and operates synchronous to the internal transmit character clock. TXCLKOx operates at either the same frequency as REFCLKx (TXRATEx = 0), or at twice the frequency of REFCLKx (TXRATEx = 1). The transmit clock outputs have no fixed phase relationship to REFCLKx. TXCLKA TXCLKB TXCLKOA TXCLKOB LVTTL Output Notes 2. When REFCLKx is configured for half-rate operation, these inputs are sampled relative to both the rising and falling edges of the associated REFCLKx. 3. When REFCLKx is configured for half-rate operation, these outputs are presented relative to both the rising and falling edges of the associated REFCLKx. Document #: 38-02101 Rev. *C Page 8 of 31 [+] Feedback CYV15G0204TRB Pin Definitions (continued) CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer Name RXDC[9:0] RXDD[9:0] I/O Characteristics Signal Description LVTTL Output, synchronous to the RXCLK output Parallel Data Output. RXDx[9:0] parallel data outputs change relative to the receive interface clock. If RXCLKx is a full-rate clock, the RXCLKx clock outputs are complementary clocks operating at the character rate. The RXDx[9:0] outputs for the associated receive channels follow rising edge of RXCLKx+ or falling edge of RXCLKx-. If RXCLKx is a half-rate clock, the RXCLKx clock outputs are complementary clocks operating at half the character rate. The RXDx[9:0] outputs for the associated receive channels follow both the falling and rising edges of the associated RXCLKx clock outputs. When BIST is enabled on the receive channel, the BIST status is presented on the RXDx[1:0] and BISTSTx outputs. See Table 6 on page 19 for each status reported by the BIST state machine. Also, while BIST is enabled, the RXDx[9:2] outputs should be ignored. BISTSTC BISTSTD LVTTL Output, synchronous to the RXCLKx output Asynchronous to reclocker output channel enable / disable BIST Status Output. When RXBISTx[1:0] = 10, BISTSTx (along with RXDx[1:0]) displays the status of the BIST reception. See Table 6 on page 19 for the BIST status reported for each combination of BISTSTx and RXDx[1:0]. When RXBISTx[1:0] 10, BISTSTx should be ignored. REPDOC REPDOD Reclocker Powered Down Status Output. REPDOx is asserted HIGH, when the associated channel's reclocker output logic is powered down. This occurs when ROE2x and ROE1x are both disabled by setting ROE2x = 0 and ROE1x = 0. Receive Path Data and Status Signals Receive Path Clock Signals TRGCLKC TRGCLKD Differential LVPECL CDR PLL Training Clock. TRGCLKx clock inputs are used as the reference source or single-ended for the frequency detector (Range Controller) of the associated receive PLL to LVTTL input clock reduce PLL acquisition time. In the presence of valid serial data, the recovered clock output of the receive CDR PLL (RXCLKx) has no frequency or phase relationship with TRGCLKx. When driven by a single-ended LVCMOS or LVTTL clock source, connect the clock source to either the true or complement TRGCLKx input, and leave the alternate TRGCLKx input open (floating). When driven by an LVPECL clock source, the clock must be a differential clock, using both inputs. RXCLKC RXCLKD LVTTL Output Clock Receive Clock Output. RXCLKx is the receive interface clock used to control timing of the RXDx[9:0] parallel outputs. These true and complement clocks are used to control timing of data output transfers. These clocks are output continuously at either the half-character rate (1/20th the serial bit-rate) or character rate (1/10th the serial bit-rate) of the data being received, as selected by RXRATEx. LVTTL Output Reclocker Clock Output. RECLKOx output clock is synthesized by the associated reclocker output PLL and operates synchronous to the internal recovered character clock. RECLKOx operates at either the same frequency as RXCLKx (RXRATEx = 0), or at twice the frequency of RXCLKx (RXRATEx = 1).The reclocker clock outputs have no fixed phase relationship to RXCLKx. Asynchronous Device Reset. RESET initializes all state machines, counters, and configuration latches in the device to a known state. RESET must be asserted LOW for a minimum pulse width. When the reset is removed, all state machines, counters and configuration latches are at an initial state. As per the JTAG specifications the device RESET cannot reset the JTAG controller. Therefore, the JTAG controller has to be reset separately. Refer to "JTAG Support" on page 19 for the methods to reset the JTAG state machine. See Table 4 on page 16 for the initialize values of the device configuration latches. RECLKOC RECLKOD Device Control Signals RESET LVTTL Input, asynchronous, internal pull-up Document #: 38-02101 Rev. *C Page 9 of 31 [+] Feedback CYV15G0204TRB Pin Definitions (continued) CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer Name LDTDEN I/O Characteristics Signal Description LVTTL Input, internal pull-up Level Detect Transition Density Enable. When LDTDEN is HIGH, the Signal Level Detector, Range Controller, and Transition Density Detector are all enabled to determine if the RXPLL tracks TRGCLKx or the selected input serial data stream. If the Signal Level Detector, Range Controller, or Transition Density Detector are out of their respective limits while LDTDEN is HIGH, the RXPLL locks to TRGCLKx until such a time they become valid. The SDASEL[A..D][1:0] inputs are used to configure the trip level of the Signal Level Detector. The Transition Density Detector limit is one transition in every 60 consecutive bits. When LDTDEN is LOW, only the Range Controller is used to determine if the RXPLL tracks TRGCLKx or the selected input serial data stream. It is recommended to set LDTDEN = HIGH. Use Local Clock. When ULCx is LOW, the RXPLL is forced to lock to TRGCLKx instead of the received serial data stream. While ULCx is LOW, the LFIx for the associated channel is LOW indicating a link fault. When ULCx is HIGH, the RXPLL performs Clock and Data Recovery functions on the input data streams. This function is used in applications in which a stable RXCLKx is needed. In cases when there is an absence of valid data transitions for a long period of time, or the high-gain differential serial inputs (INx) are left floating, there may be brief frequency excursions of the RXCLKx outputs from TRGCLKx. SPDSELA SPDSELB SPDSELC SPDSELD 3-Level Select[4] static control input Serial Rate Select. The SPDSELx inputs specify the operating signaling-rate range of each channel's transmit (channels A and B) or receive PLL (channels C and D). LOW = 195 - 400 MBd MID = 400 - 800 MBd HIGH = 800 - 1500 MBd. INSELC INSELD LVTTL Input, asynchronous Receive Input Selector. The INSELx input determines which external serial bit stream is passed to the receiver's Clock and Data Recovery circuit. When INSELx is HIGH, the Primary Differential Serial Data Input, INx1, is selected for the associated receive channel. When INSELx is LOW, the Secondary Differential Serial Data Input, INx2, is selected for the associated receive channel. Link Fault Indication Output. LFIx is an output status indicator signal. LFIx is the logical OR of six internal conditions. LFIx is asserted LOW when any of the following conditions is true: * Received serial data rate outside expected range * Analog amplitude below expected levels * Transition density lower than expected * Receive channel disabled * ULCx is LOW * Absence of TRGCLKx. Control Write Enable. The WREN input writes the values of the DATA[6:0] bus into the latch specified by the address location on the ADDR[3:0] bus.[5] Control Addressing Bus. The ADDR[3:0] bus is the input address bus used to configure the device. The WREN input writes the values of the DATA[6:0] bus into the latch specified by the address location on the ADDR[3:0] bus.[5] Table 4 on page 16 lists the configuration latches within the device, and the initialization value of the latches upon the assertion of RESET. Table 5 on page 18 shows how the latches are mapped in the device. ULCC ULCD LVTTL Input, internal pull-up LFIC LFID LVTTL Output, asynchronous Device Configuration and Control Bus Signals WREN LVTTL input, asynchronous, internal pull-up LVTTL input asynchronous, internal pull-up ADDR[3:0] Notes 4. 3-Level Select inputs are used for static configuration. These are ternary inputs that make use of logic levels of LOW, MID, and HIGH. The LOW level is usually implemented by direct connection to VSS (ground). The HIGH level is usually implemented by direct connection to VCC (power). The MID level is usually implemented by not connecting the input (left floating), which allows it to self bias to the proper level. 5. See Device Configuration and Control Interface for detailed information on the operation of the Configuration Interface. Document #: 38-02101 Rev. *C Page 10 of 31 [+] Feedback CYV15G0204TRB Pin Definitions (continued) CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer Name DATA[6:0] I/O Characteristics Signal Description LVTTL input asynchronous, internal pull-up Control Data Bus. The DATA[6:0] bus is the input data bus used to configure the device. The WREN input writes the values of the DATA[6:0] bus into the latch specified by address location on the ADDR[3:0] bus.[5] Table 4 on page 16 lists the configuration latches within the device, and the initialization value of the latches upon the assertion of RESET. Table 5 on page 18 shows how the latches are mapped in the device. Receive Clock Rate Select. Signal Detect Amplitude Select. Transmit Clock Select. Transmit PLL Clock Rate Select. Reclocker Output PLL Clock Rate Select. Receive Channel Power Control. Receive Bist Disabled. Transmit Bist Disabled. Transmitter Differential Serial Output Driver 2 Enable. Transmitter Differential Serial Output Driver 1 Enable. Reclocker Differential Serial Output Driver 2 Enable. Reclocker Differential Serial Output Driver 1 Enable. Transmit Clock Phase Alignment Buffer Reset. Factory Test 2. SCANEN2 input is for factory testing only. This input may be left as a NO CONNECT, or GND only. Factory Test 3. TMEN3 input is for factory testing only. This input may be left as a NO CONNECT, or GND only. Transmitter Primary Differential Serial Data Output. The transmitter TOUTx1 PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible connections. Transmitter Secondary Differential Serial Data Output. The transmitter TOUTx2 PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible connections. Reclocker Primary Differential Serial Data Output. The reclocker ROUTx1 PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible connections. Reclocker Secondary Differential Serial Data Output. The reclocker ROUTx2 PECL-compatible CML outputs (+3.3V referenced) are capable of driving terminated transmission lines or standard fiber-optic transmitter modules, and must be AC-coupled for PECL-compatible connections. Primary Differential Serial Data Input. The INx1 input accepts the serial data stream for deserialization. The INx1 serial stream is passed to the receive CDR circuit to extract the data content when INSELx = HIGH. Internal Device Configuration Latches RXRATE[C..D] Internal Latch[6] [6] SDASEL[2..1][C..D] Internal Latch [1:0] TXCKSEL[A..B] TXRATE[A..B] TRGRATE[C..D] RXPLLPD[C..D] RXBIST[C..D][1:0] TXBIST[A..B] TOE2[A..B] TOE1[A..B] ROE2[C..D] ROE1[C..D] PABRSTB[A..B] SCANEN2 TMEN3 Analog I/O TOUTA1 TOUTB1 Internal Latch Internal Internal Latch[6] [6] Internal Latch[6] Latch[6] [6] Internal Latch Internal Internal Internal Internal Latch[6] Latch[6] Latch[6] Latch[6] Internal Latch[6] Internal Latch[6] LVTTL input, internal pull-down LVTTL input, internal pull-down CML Differential Output Factory Test Modes TOUTA2 TOUTB2 CML Differential Output ROUTC1 ROUTD1 CML Differential Output ROUTC2 ROUTD2 CML Differential Output INC1 IND1 Differential Input Note 6. See Device Configuration and Control Interface for detailed information on the internal latches. Document #: 38-02101 Rev. *C Page 11 of 31 [+] Feedback CYV15G0204TRB Pin Definitions (continued) CYV15G0204TRB HOTLink II Dual Serializer and Dual Reclocking Deserializer Name INC2 IND2 JTAG Interface TMS TCLK TDO TDI TRST Power VCC GND +3.3V Power. Signal and Power Ground for all internal circuits. of the Phase-Align Buffer, an error is reported on that channel's TXERRx output. This output indicates an error continuously until the Phase-Align Buffer for that channel is reset. While the error remains active, the transmitter for that channel outputs a continuous "1001111000" character to indicate to the remote receiver that an error condition is present in the link. Transmit BIST Each transmit channel contains an internal pattern generator that can be used to validate both the link and device operation. These generators are enabled by the associated TXBISTx latch via the device configuration interface. When enabled, a register in the associated transmit channel becomes a signature pattern generator by logically converting to a Linear Feedback Shift Register (LFSR). This LFSR generates a 511-character sequence. This provides a predictable yet pseudo-random sequence that can be matched to an identical LFSR in the attached Receiver(s). A device reset (RESET sampled LOW) presets the BIST Enable Latches to disable BIST on both channels. All data present at the associated TXDx[9:0] inputs are ignored when BIST is active on that channel. Transmit PLL Clock Multiplier Each Transmit PLL Clock Multiplier accepts a character-rate or half-character-rate external clock at the associated REFCLKx input, and that clock is multiplied by 10 or 20 (as selected by TXRATEx) to generate a bit-rate clock for use by the transmit shifter. It also provides a character-rate clock used by the transmit paths, and outputs this character rate clock as TXCLKOx. Each clock multiplier PLL can accept a REFCLKx input between 19.5 MHz and 150 MHz, however, this clock range is limited by the operating mode of the CYV15G0204TRB clock Page 12 of 31 LVTTL Input, internal pull-up LVTTL Input, internal pull-down 3-State LVTTL Output LVTTL Input, internal pull-up LVTTL Input, internal pull-up Test Mode Select. Used to control access to the JTAG Test Modes. If maintained high for 5 TCLK cycles, the JTAG test controller is reset. JTAG Test Clock. Test Data Out. JTAG data output buffer. High-Z while JTAG test mode is not selected. Test Data In. JTAG data input port. JTAG reset signal. When asserted (LOW), this input asynchronously resets the JTAG test access port controller. I/O Characteristics Signal Description Differential Input Secondary Differential Serial Data Input. The INx2 input accepts the serial data stream for deserialization. The INx2 serial stream is passed to the receiver CDR circuit to extract the data content when INSELx = LOW. CYV15G0204TRB HOTLink II Operation The CYV15G0204TRB is a highly configurable, independent clocking, device designed to support reliable transfer of large quantities of digital video data, using high-speed serial links from multiple sources to multiple destinations. CYV15G0204TRB Transmit Data Path Input Register The parallel input bus TXDx[9:0] can be clocked in using TXCLKx (TXCKSELx = 0) or REFCLKx (TXCKSELx = 1). Phase-Align Buffer Data from each Input Register is passed to the associated Phase-Align Buffer, when the TXDx[9:0] input registers are clocked using TXCLKx (TXCKSELx = 0 and TXRATEx = 0). When the TXDx[9:0] input registers are clocked using REFCLKx (TXCKSELx = 1) and REFCLKx is a full-rate clock, the associated Phase Alignment Buffer in the transmit path is bypassed. These buffers are used to absorb clock phase differences between the TXCLKx input clock and the internal character clock for that channel. Once initialized, TXCLKx is allowed to drift in phase as much as 180 degrees. If the input phase of TXCLKx drifts beyond the handling capacity of the Phase Align Buffer, TXERRx is asserted to indicate the loss of data, and remains asserted until the Phase Align Buffer is initialized. The phase of the TXCLKx relative to its associated internal character rate clock is initialized when the configuration latch PABRSTx is written as 0. When the associated TXERRx is deasserted, the Phase Align Buffer is initialized and input characters are correctly captured. If the phase offset, between the initialized location of the input clock and REFCLKx, exceeds the skew handling capabilities Document #: 38-02101 Rev. *C [+] Feedback CYV15G0204TRB multiplier (TXRATEx) and by the level on the associated SPDSELx input. SPDSELx are 3-level select[4] inputs that select one of three operating ranges for the serial data outputs and inputs of the associated channel. The operating serial signaling-rate and allowable range of REFCLKx frequencies are listed in Table 1. Table 1. Operating Speed Settings SPDSELx LOW MID (Open) HIGH TXRATEx 1 0 1 0 1 0 REFCLKx Frequency (MHz) reserved 19.5-40 20-40 40-80 40-75 80-150 800-1500 400-800 Signaling Rate (Mbps) 195-400 Note. When a disabled transmit channel (i.e., both outputs disabled) is re-enabled: * data on the serial outputs may not meet all timing specifications for up to 250 s * the state of the phase-align buffer cannot be guaranteed, and a phase-align reset is required if the phase-align buffer is used CYV15G0204TRB Receive Data Path Serial Line Receivers Two differential Line Receivers, INx1 and INx2, are available on each channel for accepting serial data streams. The active Serial Line Receiver on a channel is selected using the associated INSELx input. The Serial Line Receiver inputs are differential, and can accommodate wire interconnect and filtering losses or transmission line attenuation greater than 16 dB. For normal operation, these inputs should receive a signal of at least VIDIFF > 100 mV, or 200 mV peak-to-peak differential. Each Line Receiver can be DC- or AC-coupled to +3.3V powered fiber-optic interface modules (any ECL/PECL family, not limited to 100K PECL) or AC-coupled to +5V powered optical modules. The common-mode tolerance of these line receivers accommodates a wide range of signal termination voltages. Each receiver provides internal DC-restoration, to the center of the receiver's common mode range, for AC-coupled signals. Signal Detect/Link Fault Each selected Line Receiver (i.e., that routed to the clock and data recovery PLL) is simultaneously monitored for * analog amplitude above amplitude level selected by SDASELx * transition density above the specified limit * range controls report the received data stream inside normal frequency range (1500 ppm[23]) * receive channel enabled * Presence of reference clock * ULCx is not asserted. All of these conditions must be valid for the Signal Detect block to indicate a valid signal is present. This status is presented on the LFIx (Link Fault Indicator) output associated with each receive channel, which changes synchronous to the receive interface clock. Analog Amplitude The REFCLKx inputs are differential inputs with each input internally biased to 1.4V. If the REFCLKx+ input is connected to a TTL, LVTTL, or LVCMOS clock source, the input signal is recognized when it passes through the internally biased reference point. When driven by a single-ended TTL, LVTTL, or LVCMOS clock source, connect the clock source to either the true or complement REFCLKx input, and leave the alternate REFCLKx input open (floating). When both the REFCLKx+ and REFCLKx- inputs are connected, the clock source must be a differential clock. This can either be a differential LVPECL clock that is DC-or AC-coupled or a differential LVTTL or LVCMOS clock. By connecting the REFCLKx- input to an external voltage source, it is possible to adjust the reference point of the REFCLKx+ input for alternate logic levels. When doing so, it is necessary to ensure that the input differential crossing point remains within the parametric range supported by the input. Transmit Serial Output Drivers The serial output interface drivers use differential Current Mode Logic (CML) drivers to provide source-matched drivers for 50 transmission lines. These drivers accept data from the Transmit Shifters. These drivers have signal swings equivalent to that of standard PECL drivers, and are capable of driving AC-coupled optical modules or transmission lines. Transmit Channels Enabled Each driver can be enabled or disabled separately via the device configuration interface. When a driver is disabled via the configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers. While most signal monitors are based on fixed constants, the analog amplitude level detection is adjustable to allow operation with highly attenuated signals, or in high-noise environments. The analog amplitude level detection is set by the SDASELx latch via device configuration interface. The SDASELx latch sets the trip point for the detection of a valid signal at one of three levels, as listed in Table 2. This control input affects the analog monitors for both receive channels. The Analog Signal Detect monitors are active for the Line Receiver as selected by the associated INSELx input. Document #: 38-02101 Rev. *C Page 13 of 31 [+] Feedback CYV15G0204TRB Table 2. Analog Amplitude Detect Valid Signal Levels[7] SDASEL Typical Signal with Peak Amplitudes Above 00 01 10 11 Analog Signal Detector is disabled 140 mV p-p differential 280 mV p-p differential 420 mV p-p differential Receive Channel Enabled The CYV15G0204TRB contains two receive channels that can be independently enabled and disabled. Each channel can be enabled or disabled separately through the RXPLLPDx input latch as controlled by the device configuration interface. When the RXPLLPDx latch = 0, the associated PLL and analog circuitry of the channel is disabled. Any disabled channel indicates a constant link fault condition on the LFIx output. When RXPLLPDx = 1, the associated PLL and receive channel is enabled to receive a serial stream. When a disabled receive channel is reenabled, the status of the associated LFIx output and data on the parallel outputs for the associated channel may be indeterminate for up to 2 ms. Clock/Data Recovery Transition Density The Transition Detection logic checks for the absence of transitions spanning greater than six transmission characters (60 bits). If no transitions are present in the data received, the Detection logic for that channel asserts LFIx. Range Controls The CDR circuit includes logic to monitor the frequency of the PLL Voltage Controlled Oscillator (VCO) used to sample the incoming data stream. This logic ensures that the VCO operates at, or near the rate of the incoming data stream for two primary cases: * when the incoming data stream resumes after a time in which it has been "missing." * when the incoming data stream is outside the acceptable signaling rate range. To perform this function, the frequency of the RXPLL VCO is periodically compared to the frequency of the TRGCLKx input. If the VCO is running at a frequency beyond 1500 ppm[23] as defined by the TRGCLKx frequency, it is periodically forced to the correct frequency (as defined by TRGCLKx, SPDSELx, and TRGRATEx) and then released in an attempt to lock to the input data stream. The sampling and relock period of the Range Control is calculated as follows: RANGE_CONTROL_ SAMPLING_PERIOD = (RECOVERED BYTE CLOCK PERIOD) * (4096). During the time that the Range Control forces the RXPLL VCO to track TRGCLKx, the LFIx output is asserted LOW. After a valid serial data stream is applied, it may take up to one RANGE CONTROL SAMPLING PERIOD before the PLL locks to the input data stream, after which LFIx should be HIGH. The operating serial signaling-rate and allowable range of TRGCLK frequencies are listed in Table 3. Table 3. Operating Speed Settings SPDSELx LOW MID (Open) HIGH TRGRATEx 1 0 1 0 1 0 TRGCLKx Frequency (MHz) reserved 19.5-40 20-40 40-80 40-75 80-150 800-1500 400-800 Signaling Rate (Mbps) 195 - 400 The extraction of a bit-rate clock and recovery of bits from each received serial stream is performed by a separate CDR block within each receive channel. The clock extraction function is performed by an integrated PLL that tracks the frequency of the transitions in the incoming bit stream and align the phase of the internal bit-rate clock to the transitions in the selected serial data stream. Each CDR accepts a character-rate (bit-rate / 10) or half-character-rate (bit-rate / 20) training clock from the associated TRGCLKx input. This TRGCLKx input is used to * ensure that the VCO (within the CDR) is operating at the correct frequency (rather than a harmonic of the bit-rate) * reduce PLL acquisition time * limit unlocked frequency excursions of the CDR VCO when there is no input data present at the selected Serial Line Receiver. Regardless of the type of signal present, the CDR attempts to recover a data stream from it. If the signalling rate of the recovered data stream is outside the limits set by the range control monitors, the CDR tracks TRGCLKx instead of the data stream. Once the CDR output (RXCLK) frequency returns back close to TRGCLKx frequency, the CDR input is switched back to the input data stream. If no data is present at the selected line receiver, this switching behavior may result in brief RXCLK frequency excursions from TRGCLKx. However, the validity of the input data stream is indicated by the LFIx output. The frequency of TRGCLKx is required to be within 1500ppm[23] of the frequency of the clock that drives the REFCLKx input of the remote transmitter to ensure a lock to the incoming data stream. This large ppm tolerance allows the CDR PLL to reliably receive a 1.485 or 1.485/1.001 Gbps SMPTE HD-SDI data stream with a constant TRGCLK frequency. For systems using multiple or redundant connections, the LFIx output can be used to select an alternate data stream. When an LFIx indication is detected, external logic can toggle selection of the associated INx1 and INx2 input through the associated INSELx input. When a port switch takes place, it is necessary for the receive PLL for that channel to reacquire the new serial stream. Note 7. The peak amplitudes listed in this table are for typical waveforms that have generally 3-4 transitions for every ten bits. In a worse case environment the signals may have a sine-wave appearance (highest transition density with repeating 0101...). Signal peak amplitudes levels within this environment type could increase the values in the table above by approximately 100 mV. Document #: 38-02101 Rev. *C Page 14 of 31 [+] Feedback CYV15G0204TRB Reclocker Each receive channel performs a reclocker function on the incoming serial data. To do this, the Clock and Data Recovery PLL first recovers the clock from the data. The data is retimed by the recovered clock and then passed to an output register. Also, the recovered character clock from the receive PLL is passed to the reclocker output PLL which generates the bit clock that is used to clock the retimed data into the output register. This data stream is then transmitted through the differential serial outputs. Reclocker Serial Output Drivers The serial output interface drivers use differential Current Mode Logic (CML) drivers to provide source-matched drivers for 50 transmission lines. These drivers accept data from the reclocker output register in the reclocker channel. These drivers have signal swings equivalent to that of standard PECL drivers, and are capable of driving AC-coupled optical modules or transmission lines. Reclocker Output Channels Enabled Each driver can be enabled or disabled separately via the device configuration interface. When a driver is disabled via the configuration interface, it is internally powered down to reduce device power. If both reclocker serial drivers for a channel are in this disabled state, the associated internal reclocker logic is also powered down. The deserialization logic and parallel outputs will remain enabled. A device reset (RESET sampled LOW) disables all output drivers. Note. When the disabled reclocker function (i.e., both outputs disabled) is re-enabled, the data on the reclocker serial outputs may not meet all timing specifications for up to 250 s. Output Bus The receive channel presents a 10-bit data signal (and a BIST status signal when RXBISTx[1:0] = 10). Receive BIST Operation Each receiver channel contains an internal pattern checker that can be used to validate both device and link operation. These pattern checkers are enabled by the associated RXBISTx[1:0] latch via the device configuration interface. When enabled, a register in the associated receive channel becomes a signature pattern generator and checker by logically converting to a Linear Feedback Shift Register (LFSR). This LFSR generates a 511-character sequence. This provides a predictable yet pseudo-random sequence that can be matched to an identical LFSR in the attached Transmitter(s). When synchronized with the received data stream, the associated Receiver checks each character from the deserializer with each character generated by the LFSR and indicates compare errors and BIST status at the RXDx[1:0] and BISTSTx bits of the Output Register. The BIST status bus {BISTSTx, RXDx[0], RXDx[1]} indicates 010b or 100b for one character period per BIST loop to indicate loop completion. This status can be used to check test pattern progress. If the number of invalid characters received ever exceeds the number of valid characters by 16, the receive BIST state Document #: 38-02101 Rev. *C machine aborts the compare operations and resets the LFSR to look for the start of the BIST sequence again. A device reset (RESET sampled LOW) presets the BIST Enable Latches to disable BIST on both channels. BIST Status State Machine When a receive path is enabled to look for and compare the received data stream with the BIST pattern, the {BISTSTx, RXDx[0], RXDx[1]} bits identify the present state of the BIST compare operation. The BIST state machine has multiple states, as shown in Figure 2 on page 20 and Table 6 on page 19. When the receive PLL detects an out-of-lock condition, the BIST state is forced to the Start-of-BIST state, regardless of the present state of the BIST state machine. If the number of detected errors ever exceeds the number of valid matches by greater than 16, the state machine is forced to the WAIT_FOR_BIST state where it monitors the receive path for the first character of the next BIST sequence. Power Control The CYV15G0204TRB supports user control of the powered up or down state of each transmit and receive channel. The receive channels are controlled by the RXPLLPDx latch via the device configuration interface. When RXPLLPDx = 0, the associated PLL and analog circuitry of the channel is disabled. The transmit channels are controlled by the TOE1x and the TOE2x latches via the device configuration interface. The reclocker function is controlled by the ROE1x and the ROE2x latches via the device configuration interface. When a driver is disabled via the configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. When the reclocker serial drivers are disabled, the reclocker function will be disabled, but the deserialization logic and parallel outputs will remain enabled. Device Reset State When the CYV15G0204TRB is reset by assertion of RESET, all state machines, counters, and configuration latches in the device are initialized to a reset state. Additionally, the JTAG controller must also be reset for valid operation (even if JTAG testing is not performed). See "JTAG Support" on page 19 for JTAG state machine initialization. See Table 4 on page 16 for the initialize values of the configuration latches. Following a device reset, it is necessary to enable the receive channels used for normal operation. This can be done by sequencing the appropriate values on the device configuration interface.[5] Device Configuration and Control Interface The CYV15G0204TRB is highly configurable via the configuration interface. The configuration interface allows each channel to be configured independently. Table 4 on page 16 lists the configuration latches within the device including the initialization value of the latches upon the assertion of RESET. Table 5 on page 18 shows how the latches are mapped in the device. Each row in the Table 5 maps to a 7-bit latch bank. Page 15 of 31 [+] Feedback CYV15G0204TRB There are 12 such write-only latch banks. When WREN = 0, the logic value in the DATA[7:0] is latched to the latch bank specified by the values in ADDR[3:0]. The second column of Table 5 specifies the channels associated with the corresponding latch bank. For example, the first three latch banks (0,1 and 2) consist of configuration bits for channel A. Latch Types There are two types of latch banks: static (S) and dynamic (D). Each channel is configured by 2 static and 1 dynamic latch banks. The S type contain those settings that normally do not change for a given application, whereas the D type controls the settings that could change during the application's lifetime. The first and second rows of each channel (address numbers 0, 1, 3, 4, 6, 7, 9, and 10) are the static control latches. The third row of latches for each channel (address numbers 2, 5, 8, and 11) are the dynamic control latches that are associated with enabling dynamic functions within the device. Static Latch Values There are some latches in the table that have a static value (i.e., 1, 0, or X). The latches that have a `1' or `0' must be configured with their corresponding value each time that their associated latch bank is configured. The latches that have an `X' are don't cares and can be configured with any value. Table 4. Device Configuration and Control Latch Descriptions Name TXCKSELA TXCKSELB Signal Description Transmit Clock Select. The initialization value of the TXCKSELx latch = 1. TXCKSELx selects the clock source used to write data into the Transmit Input Register. When TXCKSELx = 1, the associated input register TXDx[9:0] is clocked by REFCLKx. In this mode, the phase alignment buffer in the transmit path is bypassed. When TXCKSELx = 0, the associated TXCLKx is used to clock in the input register TXDx[9:0]. Transmit PLL Clock Rate Select. The initialization value of the TXRATEx latch = 0. TXRATEx is used to select the clock multiplier for the Transmit PLL. When TXRATEx = 0, each transmit PLL multiples the associated REFCLKx input by 10 to generate the serial bit-rate clock. When TXRATEx = 0, the TXCLKOx output clocks are full-rate clocks and follow the frequency and duty cycle of the associated REFCLKx input. When TXRATEx = 1, each Transmit PLL multiplies the associated REFCLKx input by 20 to generate the serial bit-rate clock. When TXRATEx = 1, the TXCLKOx output clocks are twice the frequency rate of the REFCLKx input. When TXCLKSELx = 1 and TXRATEx = 1, the Transmit Data Inputs are captured using both the rising and falling edges of REFCLKx. TXRATEx = 1 and SPDSELx = LOW, is an invalid state and this combination is reserved. Transmit Bist Disabled. The initialization value of the TXBISTx latch = 1. TXBISTx selects if the transmit BIST is disabled or enabled. When TXBISTx = 1, the transmit BIST function is disabled. When TXBISTx = 0, the transmit BIST function is enabled. Secondary Differential Serial Data Output Driver Enable. The initialization value of the TOE2x latch = 0. TOE2x selects if the TOUTx2 secondary differential output drivers are enabled or disabled. When TOE2x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When TOE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via the configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers. Primary Differential Serial Data Output Driver Enable. The initialization value of the TOE1x latch = 0. TOE1x selects if the TOUTx1 primary differential output drivers are enabled or disabled. When TOE1x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When TOE1x = 0, the associated serial data output driver is disabled. When a driver is disabled via the configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers. Transmit Clock Phase Alignment Buffer Reset. The initialization value of the PABRSTx latch = 1. The PABRSTx is used to re-center the Transmit Phase Align Buffer. When the configuration latch PABRSTx is written as a 0, the phase of the TXCLKx input clock relative to its associated REFCLKx+/- is initialized. PABRST is an asynchronous input, but is sampled by each TXCLKx to synchronize it to the internal clock domain. PABRSTx is a self clearing latch. This eliminates the requirement of writing a 1 to complete the initialization of the Phase Alignment Buffer. TXRATEA TXRATEB TXBISTA TXBISTB TOE2A TOE2B TOE1A TOE1B PABRSTA PABRSTB Document #: 38-02101 Rev. *C Page 16 of 31 [+] Feedback CYV15G0204TRB Table 4. Device Configuration and Control Latch Descriptions (continued) Name RXRATEC RXRATED Signal Description Receive Clock Rate Select. The initialization value of the RXRATEx latch = 1. RXRATEx is used to select the rate of the RXCLKx clock output. When RXRATEx = 1, the RXCLKx clock outputs are complementary clocks that follow the recovered clock operating at half the character rate. Data for the associated receive channels should be latched alternately on the rising edge of RXCLKx+ and RXCLKx-. When RXRATEx = 0, the RXCLKx clock outputs are complementary clocks that follow the recovered clock operating at the character rate. Data for the associated receive channels should be latched on the rising edge of RXCLKx+ or falling edge of RXCLKx-. Primary Serial Data Input Signal Detector Amplitude Select. The initialization value of the SDASEL1x[1:0] latch = 10. SDASEL1x[1:0] selects the trip point for the detection of a valid signal for the INx1 Primary Differential Serial Data Inputs. When SDASEL1x[1:0] = 00, the Analog Signal Detector is disabled. When SDASEL1x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV. When SDASEL1x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV. When SDASEL1x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV. Secondary Serial Data Input Signal Detector Amplitude Select. The initialization value of the SDASEL2x[1:0] latch = 10. SDASEL2x[1:0] selects the trip point for the detection of a valid signal for the INx2 Secondary Differential Serial Data Inputs. When SDASEL2x[1:0] = 00, the Analog Signal Detector is disabled When SDASEL2x[1:0] = 01, the typical p-p differential voltage threshold level is 140 mV. When SDASEL2x[1:0] = 10, the typical p-p differential voltage threshold level is 280 mV. When SDASEL2x[1:0] = 11, the typical p-p differential voltage threshold level is 420 mV. Training Clock Rate Select. The initialization value of the TRGRATEx latch = 0. TRGRATEx is used to select the clock multiplier for the training clock input to the associated CDR PLL. When TRGRATEx = 0, the TRGCLKx input is not multiplied before it is passed to the CDR PLL. When TRGRATEx = 1, the TRGCLKx input is multiplied by 2 before it is passed to the CDR PLL. TRGRATEx = 1 and SPDSELx = LOW is an invalid state and this combination is reserved. Receive Channel Enable. The initialization value of the RXPLLPDx latch = 0. RXPLLPDx selects if the associated receive channel is enabled or powered-down. When RXPLLPDx = 0, the associated receive PLL and analog circuitry are powered-down. When RXPLLPDx = 1, the associated receive PLL and analog circuitry are enabled. Receive Bist Disable / SMPTE Receive Enable. The initialization value of the RXBISTx[1:0] latch = 11. For SMPTE data reception, RXBISTx[1:0] should not remain in this initialization state (11). RXBISTx[1:0] selects if receive BIST is disabled or enabled and sets the associated channel for SMPTE data reception. When RXBISTx[1:0] = 01, the receiver BIST function is disabled and the associated channel is set to receive SMPTE data. When RXBISTx[1:0] = 10, the receive BIST function is enabled and the associated channel is set to receive BIST data. RXBISTx[1:0] = 00 and RXBISTx[1:0] = 11 are invalid states. Reclocker Secondary Differential Serial Data Output Driver Enable. The initialization value of the ROE2x latch = 0. ROE2x selects if the ROUTx2 secondary differential output drivers are enabled or disabled. When ROE2x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When ROE2x = 0, the associated serial data output driver is disabled. When a driver is disabled via the configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers. Reclocker Primary Differential Serial Data Output Driver Enable. The initialization value of the ROE1x latch = 0. ROE1x selects if the ROUTx1 primary differential output drivers are enabled or disabled. When ROE1x = 1, the associated serial data output driver is enabled allowing data to be transmitted from the transmit shifter. When ROE1x = 0, the associated serial data output driver is disabled. When a driver is disabled via the configuration interface, it is internally powered down to reduce device power. If both serial drivers for a channel are in this disabled state, the associated internal logic for that channel is also powered down. A device reset (RESET sampled LOW) disables all output drivers. SDASEL1C[1:0] SDASEL1D[1:0] SDASEL2C[1:0] SDASEL2D[1:0] TRGRATEC TRGRATED RXPLLPDC RXPLLPDD RXBISTC[1:0] RXBISTD[1:0] ROE2C ROE2D ROE1C ROE1D Document #: 38-02101 Rev. *C Page 17 of 31 [+] Feedback CYV15G0204TRB Device Configuration Strategy The following is a series of ordered events needed to load the configuration latches on a per channel basis: 1. Pulse RESET Low after device power-up. This operation resets all four channels. Initialize the JTAG state machine to its reset state as detailed in "JTAG Support" on page 19. 2. Set the static latch banks for the target channel. Table 5. Device Control Latch Configuration Table ADDR 0 (0000b) 1 (0001b) 2 (0010b) 3 (0011b) 4 (0100b) 5 (0101b) 6 (0110b) 7 (0111b) 8 (1000b) 9 (1001b) 10 (1010b) 11 (1011b) 12 (1100b) 13 (1101b) 14 (1110b) 15 (1111b) Channel A A A B B B C C C D D D Type S S D S S D S S D S S D DATA6 X X X X X X 1 SDASEL2C[1] RXBISTC[1] 1 SDASEL2D[1] RXBISTD[1] DATA5 X X X X X X 0 SDASEL2C[0] RXPLLPDC 0 SDASEL2D[0] RXPLLPDD DATA4 X X X X X X X SDASEL1C[1] RXBISTC[0] X SDASEL1D[1] RXBISTD[0] 3. Set the dynamic bank of latches for the target channel. Enable the Receive PLLs and transmit channels. If a receive channel is enabled, set the channel for SMPTE data reception (RXBISTA[1:0] = 01) or BIST data reception (RXBISTA[1:0] = 10). 4. Reset the Phase Alignment Buffer for the target channel. [Optional if phase align buffer is bypassed.] DATA3 X X TXBISTA X X TXBISTB X SDASEL1C[0] X X SDASEL1D[0] X DATA2 X 0 OE2A X 0 OE2B 0 X ROE2C 0 X ROE2D DATA1 0 TXCKSELA OE1A 0 TXCKSELB OE1B 0 X ROE1C 0 X ROE1D DATA0 X TXRATEA PABRSTA X TXRATEB PABRSTB RXRATEC TRGRATEC X RXRATED TRGRATED X Reset Value 1011111 1010110 1011001 1011111 1010110 1011001 1011111 1010110 1011001 1011111 1010110 1011001 INTERNAL TEST REGISTERS DO NOT WRITE TO THESE ADDRESSES Document #: 38-02101 Rev. *C Page 18 of 31 [+] Feedback CYV15G0204TRB JTAG Support The CYV15G0204TRB contains a JTAG port to allow system level diagnosis of device interconnect. Of the available JTAG modes, boundary scan, and bypass are supported. This capability is present only on the LVTTL inputs and outputs, the REFCLKx clock inputs, and the TRGCLKx clock inputs. The high-speed serial inputs and outputs are not part of the JTAG test chain. To ensure valid device operation after power-up (including non-JTAG operation), the JTAG state machine should also be initialized to a reset state. This should be done in addition to the device reset (using RESET). The JTAG state machine can be initialized using TRST (asserting it LOW and de-asserting it or leaving it asserted), or by asserting TMS HIGH for at least Table 6. Receive Character Status Bits 5 consecutive TCLK cycles. This is necessary in order to ensure that the JTAG controller does not enter any of the test modes after device power-up. In this JTAG reset state, the rest of the device will be in normal operation. Note. The order of device reset (using RESET) and JTAG initialization does not matter. 3-Level Select Inputs Each 3-Level select inputs reports as two bits in the scan register. These bits report the LOW, MID, and HIGH state of the associated input as 00, 10, and 11 respectively JTAG ID The JTAG device ID for the CYV15G0204TRB is `0C811069'x Description {BISTSTx, RXDx[0], RXDx[1]} 000, 001 010 011 100 101 110 111 Receive BIST Status (Receive BIST = Enabled) BIST Data Compare. Character compared correctly. BIST Last Good. Last Character of BIST sequence detected and valid. Reserved. BIST Last Bad. Last Character of BIST sequence detected invalid. BIST Start. Receive BIST is enabled on this channel, but character compares have not yet commenced. This also indicates a PLL Out of Lock condition. BIST Error. While comparing characters, a mismatch was found in one or more of the character bits. BIST Wait. The receiver is comparing characters. but has not yet found the start of BIST character to enable the LFSR. Document #: 38-02101 Rev. *C Page 19 of 31 [+] Feedback CYV15G0204TRB Figure 2. Receive BIST State Machine Monitor Data Received Receive BIST {BISTSTx, RXDx[0], Detected LOW RXDx[1]} = BIST_START (101) RX PLL Out of Lock {BISTSTx, RXDx[0], RXDx[1]} = BIST_WAIT (111) No Start of BIST Detected Yes, {BISTSTx, RXDx[0], RXDx[1]} = BIST_DATA_COMPARE (000, 001) Compare Next Character Mismatch Yes Auto-Abort Condition Match {BISTSTx, RXDx[0], RXDx[1]} = BIST_DATA_COMPARE (000, 001) No End-of-BIST State End-of-BIST State No Yes, {BISTSTx, RXDx[0], RXDx[1]} = BIST_LAST_BAD (100) Yes, {BISTSTx, RXDx[0], RXDx[1]} = BIST_LAST_GOOD (010) No, {BISTSTx, RXDx[0], RXDx[1]} = BIST_ERROR (110) Document #: 38-02101 Rev. *C Page 20 of 31 [+] Feedback CYV15G0204TRB Maximum Ratings (Above which the useful life may be impaired. User guidelines only, not tested.) Storage Temperature .................................. -65C to +150C Ambient Temperature with Power Applied............................................. -55C to +125C Supply Voltage to Ground Potential ............... -0.5V to +3.8V DC Voltage Applied to LVTTL Outputs in High-Z State .......................................-0.5V to VCC + 0.5V Output Current into LVTTL Outputs (LOW)..................60 mA DC Input Voltage....................................-0.5V to VCC + 0.5V Static Discharge Voltage.......................................... > 2000 V (per MIL-STD-883, Method 3015) Latch-up Current..................................................... > 200 mA Power-up Requirements The CYV15G0204TRB requires one power-supply. The Voltage on any input or I/O pin cannot exceed the power pin during power-up. Operating Range Range Commercial Ambient Temperature 0C to +70C VCC +3.3V 5% CYV15G0204TRB DC Electrical Characteristics Parameter LVTTL-compatible Outputs VOHT VOLT IOST IOZL VIHT VILT IIHT IILT IIHPDT IILPUT VDIFF[9] VIHHP VILLP Output HIGH Voltage Output LOW Voltage Output Short Circuit Current High-Z Output Leakage Current Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Input HIGH Current with internal pull-down Input LOW Current with internal pull-up Input Differential Voltage Highest Input HIGH Voltage Lowest Input LOW voltage REFCLKx Input, VIN = VCC Other Inputs, VIN = VCC REFCLKx Input, VIN = 0.0V Other Inputs, VIN = 0.0V VIN = VCC VIN = 0.0V 400 1.2 0.0 1.0 Min. VCC Max. Min. VCC Max. Min. VCC Max. VIN = VCC VIN = VCC/2 VIN = GND -50 0.87 * VCC 0.47 * VCC 0.0 IOH = - 4 mA, VCC = Min. IOL = 4 mA, VCC = Min. VOUT = 0V[8], VCC = 3.3V VOUT = 0V, VCC -20 -20 2.0 -0.5 2.4 0.4 -100 20 VCC + 0.3 0.8 1.5 +40 -1.5 -40 +200 -200 VCC VCC VCC/2 VCC - 1.2V VCC 0.53 * VCC 0.13 * VCC 200 50 -200 V V mA A V V mA A mA A A A mV V V V V V V A A A Description Test Conditions Min. Max. Unit LVTTL-compatible Inputs LVDIFF Inputs: REFCLKx VCOMREF[10] Common Mode Range 3-Level Inputs VIHH VIMM VILL IIHH IIMM IILL Three-Level Input HIGH Voltage Three-Level Input MID Voltage Three-Level Input LOW Voltage Input HIGH Current Input MID current Input LOW current Notes 8. Tested one output at a time, output shorted for less than one second, less than 10% duty cycle. 9. This is the minimum difference in voltage between the true and complement inputs required to ensure detection of a logic-1 or logic-0. A logic-1 exists when the true (+) input is more positive than the complement (-) input. A logic-0 exists when the complement (-) input is more positive than true (+) input. 10. The common mode range defines the allowable range of REFCLKx+ and REFCLKx- when REFCLKx+ = REFCLKx-. This marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0. Document #: 38-02101 Rev. *C Page 21 of 31 [+] Feedback CYV15G0204TRB CYV15G0204TRB DC Electrical Characteristics (continued) Parameter VOHC VOLC VODIF Description Output HIGH Voltage (Vcc Referenced) Output LOW Voltage (VCC Referenced) Output Differential Voltage |(OUT+) - (OUT-)| Input Differential Voltage |(IN+) - (IN-)| Highest Input HIGH Voltage Lowest Input LOW Voltage Input HIGH Current Input LOW Current Common Mode input range VIN = VIHE Max. VIN = VILE Min. ((VCC - 2.0V)+0.5)min, (VCC - 0.5V) max. REFCLKx = Commercial MAX REFCLKx = Commercial 125 MHz -700 +1.25 Typ. 810 770 +3.1 Max. 990 950 mA mA VCC - 2.0 1350 Test Conditions 100 differential load 150 differential load 100 differential load 150 differential load 100 differential load 150 differential load Min. VCC - 0.5 VCC - 0.5 VCC - 1.4 VCC - 1.4 450 560 100 Max. VCC - 0.2 VCC - 0.2 VCC - 0.7 VCC - 0.7 900 1000 1200 VCC Unit V V V V mV mV mV V V A A V Differential CML Serial Outputs: TOUTA1, TOUTA2, TOUTB1, TOUTB2, ROUTC1, ROUTC2, ROUTD1, ROUTD2 Differential Serial Line Receiver Inputs: INC1, INC2, IND1, IND2 VDIFFs[9] VIHE VILE IIHE IILE VICOM[11] Power Supply ICC [12, 13] ICC [12, 13] Max Power Supply Current Typical Power Supply Current AC Test Loads and Waveforms 3.3V R1 R1 = 590 R2 = 435 CL CL 7 pF (Includes fixture and probe capacitance) RL = 100 (Includes fixture and probe capacitance) RL R2 [14] (b) CML Output Test Load [14] (a) LVTTL Output Test Load 3.0V Vth = 1.4V GND 1 ns 2.0V 0.8V 2.0V 0.8V VIHE Vth = 1.4V VILE 1 ns 20% VIHE 80% VILE 80% 20% 270 ps 270 ps (c) LVTTL Input Test Waveform [15] (d) CML/LVPECL Input Test Waveform Notes 11. The common mode range defines the allowable range of INPUT+ and INPUT- when INPUT+ = INPUT-. This marks the zero-crossing between the true and complement inputs as the signal switches between a logic-1 and a logic-0. 12. Maximum ICC is measured with VCC = MAX, TA = 25C, with all channels and Serial Line Drivers enabled, sending a continuous alternating 01 pattern, and outputs unloaded. 13. Typical ICC is measured under similar conditions except with VCC = 3.3V, TA = 25C, with all channels enabled and one Serial Line Driver per transmit channel sending a continuous alternating 01 pattern. The redundant outputs on each channel are powered down and the parallel outputs are unloaded. 14. Cypress uses constant current (ATE) load configurations and forcing functions. This figure is for reference only. 15. The LVTTL switching threshold is 1.4V. All timing references are made relative to where the signal edges cross the threshold voltage. Document #: 38-02101 Rev. *C Page 22 of 31 [+] Feedback CYV15G0204TRB CYV15G0204TRB AC Electrical Characteristics Parameter fTS tTXCLK tTXCLKH[16] tTXCLKL[16] tTXCLKR [16, 17, 18, 19] tTXCLKF [16, 17, 18, 19] tTXDS tTXDH fTOS tTXCLKO tTXCLKOD fRS tRXCLKP tRXCLKD tRXCLKR [16] tRXCLKF [16] tRXDv-[20] tRXDv+[20] fROS tRECLKO tRECLKOD fREF tREFCLK tREFH tREFL Description TXCLKx Clock Cycle Frequency TXCLKx Period=1/fTS TXCLKx HIGH Time TXCLKx LOW Time TXCLKx Rise Time TXCLKx Fall Time Transmit Data Set-up Time to TXCLKx (TXCKSELx = 0) Transmit Data Hold Time from TXCLKx (TXCKSELx = 0) TXCLKOx Clock Frequency = 1x or 2x REFCLKx Frequency TXCLKOx Period=1/fTOS TXCLKO Duty Cycle centered at 60% HIGH time RXCLKx Clock Output Frequency RXCLKx Period = 1/fRS RXCLKx Duty Cycle Centered at 50% (Full Rate and Half Rate) RXCLKx Rise Time RXCLKx Fall Time Status and Data Valid Time to RXCLKx (RXRATEx = 0) (Full Rate) Status and Data Valid Time to RXCLKx (RXRATEx = 1) (Half Rate) Status and Data Valid Time to RXCLKx (RXRATEx = 0) Status and Data Valid Time to RXCLKx (RXRATEx = 1) RECLKOx Clock Frequency RECLKOx Period=1/fROS RECLKOx Duty Cycle centered at 60% HIGH time REFCLKx Clock Frequency REFCLKx Period = 1/fREF REFCLKx HIGH Time (TXRATEx = 1)(Half Rate) REFCLKx HIGH Time (TXRATEx = 0)(Full Rate) REFCLKx LOW Time (TXRATEx = 1)(Half Rate) REFCLKx LOW Time (TXRATEx = 0)(Full Rate) Min. 19.5 6.66 2.2 2.2 0.2 0.2 2.2 1.0 19.5 6.66 -1.9 9.75 6.66 -1.0 0.3 0.3 5UI-2.0[21] 5UI-1.3[21] 5UI-1.8[21] 5UI-2.6[21] 19.5 6.66 -1.9 19.5 6.6 5.9 2.9[16] 5.9 2.9[16] 150 51.28 0 150 51.28 150 51.28 0 150 102.56 +1.0 1.2 1.2 1.7 1.7 Max 150 51.28 Unit MHz ns ns ns ns ns ns ns MHz ns ns MHz ns ns ns ns ns ns ns ns MHz ns ns MHz ns ns ns ns ns CYV15G0204TRB Transmitter LVTTL Switching Characteristics Over the Operating Range CYV15G0204TRB Receiver LVTTL Switching Characteristics Over the Operating Range CYV15G0204TRB REFCLKx Switching Characteristics Over the Operating Range tREFD[22] REFCLKx Duty Cycle 30 70 % tREFR [16, 17, 18, 19] REFCLKx Rise Time (20%-80%) 2 ns tREFF[16, 17, 18, 19] REFCLKx Fall Time (20%-80%) 2 ns tREFRX[23] TRGCLKx Frequency Referenced to Received Clock Period -0.15 +0.15 % Notes 16. Tested initially and after any design or process changes that may affect these parameters, but not 100% tested. 17. The ratio of rise time to falling time must not vary by greater than 2:1. 18. For a given operating frequency, neither rise or fall specification can be greater than 20% of the clock-cycle period or the data sheet maximum time. 19. All transmit AC timing parameters measured with 1-ns typical rise time and fall time. 20. Parallel data output specifications are only valid if all outputs are loaded with similar DC and AC loads. 21. Receiver UI (Unit Interval) is calculated as 1/(fREF * 20) (when TRGRATEx = 1) or 1/(fREF * 10) (when TRGRATEx = 0). In an operating link this is equivalent to tB. 22. The duty cycle specification is a simultaneous condition with the tREFH and tREFL parameters. This means that at faster character rates the REFCLKx duty cycle cannot be as large as 30%-70%. 23. TRGCLKx has no phase or frequency relationship with the recovered clock(s) and only acts as a centering reference to reduce clock synchronization time. TRGCLKx must be within 1500 PPM (0.15%) of the transmitter PLL reference (REFCLKx) frequency. Although transmitting to a HOTLink II receiver channel necessitates the frequency difference between the transmitter and receiver reference clocks to be within 1500-PPM, the stability of the crystal needs to be within the limits specified by the appropriate standard when transmitting to a remote receiver that is compliant to that standard. Document #: 38-02101 Rev. *C Page 23 of 31 [+] Feedback CYV15G0204TRB CYV15G0204TRB AC Electrical Characteristics (continued) Parameter tTREFDS Description Transmit Data Set-up Time to REFCLKx - Full Rate (TXRATEx = 0, TXCKSELx = 1) Transmit Data Set-up Time to REFCLKx - Half Rate (TXRATEx = 1, TXCKSELx = 1) tTREFDH Transmit Data Hold Time from REFCLKx - Full Rate (TXRATEx = 0, TXCKSELx = 1) Transmit Data Hold Time from REFCLKx - Half Rate (TXRATEx = 1, TXCKSELx = 1) CYV15G0204TRB TRGCLKx Switching Characteristics Over the Operating Range fREF tREFCLK tREFH tREFL tREFD[22] tREFR [16, 17, 18, 19] tREFF[16, 17, 18, 19] tREFRX[23] tDATAH tDATAS tWRENP fTCLK tTCLK tRST Parameter tB tRISE[16] Bit Time CML Output Rise Time 20-80% (CML Test Load) SPDSELx = HIGH SPDSELx= MID SPDSELx =LOW tFALL[16] CML Output Fall Time 80-20% (CML Test Load) SPDSELx = HIGH SPDSELx = MID SPDSELx =LOW TRGCLKx Clock Frequency TRGCLKx Period = 1/fREF TRGCLKx HIGH Time (TXRATEx = 1)(Half Rate) TRGCLKx HIGH Time (TXRATEx = 0)(Full Rate) TRGCLKx LOW Time (TXRATEx = 1)(Half Rate) TRGCLKx LOW Time (TXRATEx = 0)(Full Rate) TRGCLKx Duty Cycle TRGCLKx Rise Time (20%-80%) TRGCLKx Fall Time (20%-80%) TRGCLKx Frequency Referenced to Received Clock Frequency Bus Configuration Data Hold Bus Configuration Data Setup Bus Configuration WREN Pulse Width JTAG Test Clock Frequency JTAG Test Clock Period Device RESET Pulse Width Description Condition 50 30 Min. 660 50 100 180 50 100 180 Max. 5128 270 500 1000 270 500 1000 -0.15 0 10 10 20 19.5 6.6 5.9 2.9[16] 5.9 2.9[16] 30 70 2 2 +0.15 150 51.28 MHz ns ns ns ns ns % ns ns % ns ns ns MHz ns ns Unit ps ps ps ps ps ps ps Min. 2.4 2.3 1.0 1.6 Max Unit ns ns ns ns CYV15G0204TRB Bus Configuration Write Timing Characteristics Over the Operating Range CYV15G0204TRB JTAG Test Clock Characteristics Over the Operating Range CYV15G0204TRB Device RESET Characteristics Over the Operating Range CYV15G0204TRB Transmitter and Reclocker Serial Output Characteristics Over the Operating Range Document #: 38-02101 Rev. *C Page 24 of 31 [+] Feedback CYV15G0204TRB PLL Characteristics Parameter tJTGENSD[16, 24] tJTGENHD[16, 24] tTXLOCK tJRGENSD[16, 25] tJRGENHD[16, 25] tRXLOCK tRXUNLOCK Description Transmit Jitter Generation - SD Data Rate Transmit Jitter Generation - HD Data Rate Transmit PLL lock to REFCLKx Reclocker Jitter Generation - SD Data Rate Reclocker Jitter Generation - HD Data Rate TRGCLKx = 27 MHz TRGCLKx = 148.5 MHz 133 107 376k 376k 46 Condition REFCLKx = 27 MHz REFCLKx = 148.5 MHz Min. Typ. 200 76 200 Max. Unit ps ps s ps ps UI UI UI CYV15G0204TRB Transmitter Output PLL Characteristics CYV15G0204TRB Reclocker Output PLL Characteristics CYV15G0204TRB Receive PLL Characteristics Over the Operating Range Receive PLL lock to input data stream (cold start) Receive PLL lock to input data stream Receive PLL Unlock Rate Capacitance[16] Parameter CINTTL CINPECL Description TTL Input Capacitance PECL input Capacitance Test Conditions TA = 25C, f0 = 1 MHz, VCC = 3.3V TA = 25C, f0 = 1 MHz, VCC = 3.3V \ Max. 7 4 Unit pF pF CYV15G0204TRB HOTLink II Transmitter Switching Waveforms Transmit Interface Write Timing TXCLKx selected TXCLKx tTXCLK tTXCLKH tTXCLKL tTXDS TXDx[9:0] tTXDH Transmit Interface Write Timing REFCLKx selected TXRATEx = 0 REFCLKx tREFCLK tREFH tREFL tTREFDS TXDx[9:0], tTREFDH Notes 24. While sending BIST data at the corresponding data rate, after 10,000 histogram hits, time referenced to REFCLKx input. 25. Receiver input stream is BIST data from the transmit channel. This data is reclocked and output to a wide-bandwidth digital sampling oscilloscope. The measurement was recorded after 10,000 histogram hits, time referenced to REFCLKx of the transmit channel. Document #: 38-02101 Rev. *C Page 25 of 31 [+] Feedback CYV15G0204TRB CYV15G0204TRB HOTLink II Transmitter Switching Waveforms (continued) Transmit Interface Write Timing REFCLKx selected TXRATEx = 1 REFCLKx Note 26 tREFCLK tREFH tREFL tTREFDS TXDx[9:0] tTREFDH tTREFDS tTREFDH Transmit Interface TXCLKOx Timing TXRATEx = 1 REFCLKx tREFCLK tREFH tREFL Note 27 tTXCLKO Note 28 TXCLKOx (internal) Transmit Interface TXCLKOx Timing tREFH TXRATEx = 0 REFCLKx tREFCLK tREFL Note27 tTXCLKO Note28 TXCLKOx Notes 26. When REFCLKx is configured for half-rate operation (TXRATEx = 1) and data is captured using REFCLKx instead of a TXCLKx clock. Data is captured using both the rising and falling edges of REFCLKx. 27. The TXCLKOx output remains at the character rate regardless of the state of TXRATEx and does not follow the duty cycle of REFCLKx. 28. The rising edge of TXCLKOx output has no direct phase relationship to the REFCLKx input. Document #: 38-02101 Rev. *C Page 26 of 31 [+] Feedback CYV15G0204TRB Switching Waveforms for the CYV15G0204TRB HOTLink II Receiver Receive Interface Read Timing RXRATEx = 0 RXCLKx+ tRXCLKP RXCLKx- tRXDV- RXDx[9:0] tRXDV+ Receive Interface Read Timing RXRATEx = 1 RXCLKx+ tRXCLKP RXCLKx- tRXDV- RXDx[9:0] tRXDV+ Bus Configuration Write Timing ADDR[3:0] DATA[6:0] tWRENP WREN tDATAS tDATAH Document #: 38-02101 Rev. *C Page 27 of 31 [+] Feedback CYV15G0204TRB Table 7. Package Coordinate Signal Allocation Ball ID A01 A02 A03 A04 A05 A06 A07 A08 A09 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 B01 B02 B03 B04 B05 B06 B07 B08 B09 B10 B11 B12 B13 B14 B15 B16 B17 B18 B19 B20 C01 C02 C03 Signal Name INC1- ROUTC1- INC2- ROUTC2- VCC IND1- ROUTD1- GND IND2- ROUTD2- GND TOUTA1- GND GND TOUTA2- VCC VCC TOUTB1- VCC TOUTB2- INC1+ ROUTC1+ INC2+ ROUTC2+ VCC IND1+ ROUTD1+ GND IND2+ ROUTD2+ NC TOUTA1+ GND NC TOUTA2+ VCC NC TOUTB1+ NC TOUTB2+ TDI TMS INSELC Signal Type CML IN CML OUT CML IN CML OUT POWER CML IN CML OUT GROUND CML IN CML OUT GROUND CML OUT GROUND GROUND CML OUT POWER POWER CML OUT POWER CML OUT CML IN CML OUT CML IN CML OUT POWER CML IN CML OUT GROUND CML IN CML OUT NO CONNECT CML OUT GROUND NO CONNECT CML OUT POWER NO CONNECT CML OUT NO CONNECT CML OUT LVTTL IN PU LVTTL IN PU LVTTL IN Ball ID C07 C08 C09 C10 C11 C12 C13 C14 C15 C16 C17 C18 C19 C20 D01 D02 D03 D04 D05 D06 D07 D08 D09 D10 D11 D12 D13 D14 D15 D16 D17 D18 D19 D20 E01 E02 E03 E04 E17 E18 E19 E20 F01 Signal Name ULCC GND DATA[6] DATA[4] DATA[2] DATA[0] GND NC SPDSELD VCC LDTDEN TRST GND TDO TCLK RESET INSELD VCC VCC VCC SPDSELC GND DATA[5] DATA[3] DATA[1] GND GND GND NC VCC NC VCC SCANEN2 TMEN3 VCC VCC VCC VCC VCC VCC VCC VCC RXDC[8] Signal Type LVTTL IN PU GROUND LVTTL IN PU LVTTL IN PU LVTTL IN PU LVTTL IN PU GROUND NO CONNECT 3-LEVEL SEL POWER LVTTL IN PU LVTTL IN PU GROUND LVTTL 3-S OUT LVTTL IN PD LVTTL IN PU LVTTL IN POWER POWER POWER 3-LEVEL SEL GROUND LVTTL IN PU LVTTL IN PU LVTTL IN PU GROUND GROUND GROUND NO CONNECT POWER NO CONNECT POWER LVTTL IN PD LVTTL IN PD POWER POWER POWER POWER POWER POWER POWER POWER LVTTL OUT Ball ID F17 F18 F19 F20 G01 G02 G03 G04 G17 G18 G19 G20 H01 H02 H03 H04 H17 H18 H19 H20 J01 J02 J03 J04 J17 J18 J19 J20 K01 K02 K03 K04 K17 K18 K19 K20 L01 L02 L03 L04 L17 L18 L19 Signal Name NC NC TXCLKOB NC GND WREN GND GND SPDSELB NC SPDSELA NC GND GND GND GND GND GND GND GND GND GND GND GND NC NC NC NC RXDC[4] TRGCLKC- GND GND NC NC NC NC RXDC[5] TRGCLKC+ LFIC GND NC NC NC Signal Type NO CONNECT NO CONNECT LVTTL OUT NO CONNECT GROUND LVTTL IN PU GROUND GROUND 3-LEVEL SEL NO CONNECT 3-LEVEL SEL NO CONNECT GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND NO CONNECT NO CONNECT NO CONNECT NO CONNECT LVTTL OUT PECL IN GROUND GROUND NO CONNECT NO CONNECT NO CONNECT NO CONNECT LVTTL OUT PECL IN LVTTL OUT GROUND NO CONNECT NO CONNECT NO CONNECT Page 28 of 31 Document #: 38-02101 Rev. *C [+] Feedback CYV15G0204TRB Table 7. Package Coordinate Signal Allocation (continued) Ball ID C04 C05 C06 M03 M04 M17 M18 M19 M20 N01 N02 N03 N04 N17 N18 N19 N20 P01 P02 P03 P04 P17 P18 P19 P20 R01 R02 R03 R04 R17 R18 R19 R20 T01 T02 T03 T04 T17 T18 T19 T20 U01 U02 Signal Name VCC VCC ULCD VCC REPDOC REFCLKB+ REFCLKB- TXERRB TXCLKB GND GND GND GND GND GND GND GND RXDC[3] RXDC[2] RXDC[1] RXDC[0] TXDB[5] TXDB[4] TXDB[3] TXDB[2] BISTSTC RECLKOC RXCLKC+ RXCLKC- TXDB[1] TXDB[0] TXDB[9] TXDB[7] VCC VCC VCC VCC VCC VCC VCC VCC VCC VCC Signal Type POWER POWER LVTTL IN PU POWER LVTTL OUT PECL IN PECL IN LVTTL OUT LVTTL IN PD GROUND GROUND GROUND GROUND GROUND GROUND GROUND GROUND LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT LVTTL IN LVTTL IN LVTTL IN LVTTL IN LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT LVTTL IN LVTTL IN LVTTL IN LVTTL IN POWER POWER POWER POWER POWER POWER POWER POWER POWER POWER Ball ID F02 F03 F04 U03 U04 U05 U06 U07 U08 U09 U10 U11 U12 U13 U14 U15 U16 U17 U18 U19 U20 V01 V02 V03 V04 V05 V06 V07 V08 V09 V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 W01 W02 Signal Name RXDC[9] VCC VCC VCC VCC VCC RXDD[4] RXDD[3] GND TXDA[9] ADDR [0] TRGCLKD- TXDA[1] GND TXDA[4] TXDA[8] VCC NC TXDB[8] NC NC VCC VCC VCC RXDD[8] VCC RXDD[5] RXDD[1] GND BISTSTD ADDR [2] TRGCLKD+ TXCLKOA GND TXDA[3] TXDA[7] VCC NC NC NC NC VCC VCC Signal Type LVTTL OUT POWER POWER POWER POWER POWER LVTTL OUT LVTTL OUT GROUND LVTTL IN LVTTL IN PU PECL IN LVTTL IN GROUND LVTTL IN LVTTL IN POWER NO CONNECT LVTTL IN NO CONNECT NO CONNECT POWER POWER POWER LVTTL OUT POWER LVTTL OUT LVTTL OUT GROUND LVTTL OUT LVTTL IN PU PECL IN LVTTL OUT GROUND LVTTL IN LVTTL IN POWER NO CONNECT NO CONNECT NO CONNECT NO CONNECT POWER POWER Page 29 of 31 Ball ID L20 M01 M02 W03 W04 W05 W06 W07 W08 W09 W10 W11 W12 W13 W14 W15 W16 W17 W18 W19 W20 Y01 Y02 Y03 Y04 Y05 Y06 Y07 Y08 Y09 Y10 Y11 Y12 Y13 Y14 Y15 Y16 Y17 Y18 Y19 Y20 Signal Name TXDB[6] RXDC[6] RXDC[7] LFID RXCLKD- VCC RXDD[6] RXDD[0] GND ADDR [3] ADDR [1] NC TXERRA GND TXDA[2] TXDA[6] VCC NC REFCLKA+ NC NC VCC VCC RXDD[9] RXCLKD+ VCC RXDD[7] RXDD[2] GND RECLKOD NC TXCLKA NC GND TXDA[0] TXDA[5] VCC REPDOD REFCLKA- NC NC Signal Type LVTTL IN LVTTL OUT LVTTL OUT LVTTL OUT LVTTL OUT POWER LVTTL OUT LVTTL OUT GROUND LVTTL IN PU LVTTL IN PU NO CONNECT LVTTL OUT GROUND LVTTL IN LVTTL IN POWER NO CONNECT PECL IN NO CONNECT NO CONNECT POWER POWER LVTTL OUT LVTTL OUT POWER LVTTL OUT LVTTL OUT GROUND LVTTL OUT NO CONNECT LVTTL IN PD NO CONNECT GROUND LVTTL IN LVTTL IN POWER LVTTL OUT PECL IN NO CONNECT NO CONNECT Document #: 38-02101 Rev. *C [+] Feedback CYV15G0204TRB Ordering Information Speed Standard Standard Ordering Code CYV15G0204TRB-BGC CYV15G0204TRB-BGXC Package Name BL256 BL256 Package Type 256-Ball Thermally Enhanced Ball Grid Array Pb-Free 256-Ball Thermally Enhanced Ball Grid Array Operating Range Commercial Commercial Package Diagram Figure 3. 256-Lead L2 Ball Grid Array (27 x 27 x 1.57 mm) BL256 TOP VIEW 27.000.13 A1 CORNER I.D. 0.20(4X) A O0.15 M C O0.30 M C O0.750.15(256X) 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P R T U V W Y BOTTOM VIEW (BALL SIDE) A B 24.13 A1 CORNER I.D. R 2.5 Max (4X) 27.000.13 12.065 1.27 24.13 A B 1.570.175 0.97 REF. 0.15 C 0.50 MIN. A 0.600.10 C 26 TYP. 0.15 C SEATING PLANE 0.20 MIN TOP OF MOLD COMPOUND TO TOP OF BALLS SIDE VIEW SECTION A-A 51-85123-*E HOTLink is a registered trademark and HOTLink II is a trademark of Cypress Semiconductor. All product and company names mentioned in this document may be the trademarks of their respective holders. Document #: 38-02101 Rev. *C Page 30 of 31 (c) Cypress Semiconductor Corporation, 2002-2007. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges. [+] Feedback CYV15G0204TRB Document History Page Document Title: CYV15G0204TRB Independent Clock HOTLink IITM Dual Serializer and Dual Reclocking Deserializer Document Number: 38-02101 REV. ** *A *B *C ECN NO. 244348 338721 384307 1034060 ISSUE DATE See ECN See ECN See ECN See ECN ORIG. OF CHANGE FRE SUA AGT UKK New Data Sheet Added Pb-Free package option availability Revised setup and hold times (tTXDH, tTREFDS, tTREFDH, tRXDv-, tRXDv+) Added clarification for the necessity of JTAG controller reset and the methods to implement it. DESCRIPTION OF CHANGE Document #: 38-02101 Rev. *C Page 31 of 31 [+] Feedback |
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